A phase-locked loop (PLL) is often used to generate clock signals. As well known in the art, a PLL is an electronic circuit that oscillates at a desired frequency and automatically adjusts the phase of its oscillation to match (lock on) that of an input signal. The PLL includes an oscillator, which is often a voltage-controlled oscillator (VCO). A VCO typically includes inverters configured in a ring. An odd number of inverters is needed to oscillate.
In addition to the VCO, a conventional PLL may include a phase/frequency detector to convert a phase difference to a pulse width modulated (PWM) error signal, a charge pump and lag lead loop filter to convert the phase error to a control voltage and a buffer amplifier that converts the high impedance control voltage to a low impedance drive for a VCO tune line. The VCO converts the control voltage to an output phase. A programmable divider at the VCO output feeds the divided-down VCO phase back to the phase detector input to complete the loop.
In general, a PLL operates by converting a pulsed error voltage to a DC voltage that is used to control the VCO. This DC control voltage causes the VCO to slightly change the output signal of the VCO in a direction that reduces the phase difference and also the frequency difference between the input and output signals. This error correcting cycle is repeated for each reference frequency cycle period, ultimately resulting in a minimum difference between the two frequencies. The phase locked loop is described as “locked” when the phase difference between the two signals has stabilized.
Sensing the voltage tune line provides valuable information about how a PLL is operating. For example, access to a voltage tune line in test allows a VCO tune curve to be tested, frequency step response to be measured for stability, frequency acquisition to be measured for power up lock time, the lock range to be measure, and coupled spurious signals to be measured.
The voltage tune line of the VCO in a PLL with a charge pump, however, is a sensitive point to probe. For example, for a 10 GHz/V VCO gain and a 10 MHz modulation frequency, a coupled voltage level due to a voltage tune line probe should be less than 1uV in order to maintain a sideband level less than −60dBc. Additionally, extending a line out from the voltage tune line to a test pad, or port, in a system on a chip provides a path for signals to be coupled to a voltage tune line. This is evident in a PLL with a charge pump that presents a high impedance point connection to the PLL. Consequently, direct contact with the voltage tune line can couple in spurious signals to the PLL and shift a phase error thereof so that reference sidebands get significantly larger. All of these effects can cause jitter at an output of the PLL.
Accordingly, what is needed in the art is a system and method to assess the voltage tune line of a PLL to obtain measurements with a reduced disturbance to the PLL. What is also needed in the art is a system and method to assess the voltage tune line of a PLL to obtain measurements with minimal disturbance to the PLL.